? 2002 california micro devices corp. all rights reserved. 02/14/02 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com 1 PACVGA100/101 vga port esd protection and termination network features ? seven channel esd protection + 15 kv esd protection per channel, c onnector side (hbm) + 8 kv contact, 15 kv air discharge esd protection per channel, connector side (iec 61000-4-2 level 4 standard) low loading capacitance?4.5pf typical 16-pin qsop package applications esd protection and termination resistors for vga (video) port interfaces desktop pcs notebook computers lcd monitors product description the PACVGA100/101 functions as a transmission line termination and esd protection device for vi deo appli- cations. it provides 75 ohm parallel terminations for video r, g, and b lines and series terminations for the horizontal sync, vertical sync and the two ddc lines which serve as plug and play logic signals. in addition, all interface lines provide level 4 esd protection per the iec 61000-4-2 contact discharge specification. the PACVGA100 provides internal pull-up resistors (r3) for the two ddc lines whereas the pacvga101 omits these internal pull-ups so that different pull-up resistor values can be added externally. simplified electrical schematic typical application circuit r1 = 75 ?, r2 = 33 ? r3 = 2.2k ? (for PACVGA100 only) * r3 omitted for pacvga101 red r1 r2 2 3 5 7 9 11 14 413 15 12 10 6 16 8 1 0.2uf c bypass v cc v cc video connector video controller r1, r2 required only for vga101 h-sync v- s yn c ddc_data ddc_clk blue grn h-sync v- sync ddc_data ddc_clk r g b PACVGA100/101 note 1: for best esd protection, minimize r/g/b trace lengths between the PACVGA100/101 device and the v ideo (see note 1) connector.
? 2002 california micro devices corp. all rights reserved. 2 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com 02/14/02 PACVGA100/101 pin descriptions lead(s) name description 1, 8, 16 v cc positive voltage supply pins. 2 rgb1 rgb video protection channel 1. ties to one of the rgb video lines ( for example, the red signal) between the vga controller device and the video connector. 3 rgb2 rgb video protection channel 2. ties to one of the rgb video lines ( for example, the blue signal) between the vga controller device and the video connector. 4, 13 v ss ground reference supply pin. 5 rgb3 rgb video protection channel 3. ties to one of the rgb video lines ( for example, the green signal) between the vga controller device and the video connector. 6 sync1_conn sync signal output 1. ties to the video connector side of one of the sync lines (for example the horizontal sync signal). 7 sync1_ctlr sync signal input 1. connects to the vga controller side of one of the sync lines (for example, the horizontal sync signal). 9 sync2_ctlr sync signal input 2. connects to the vga controller side of one of the sync lines (for example, the vertical sync signal). 10 sync2_conn sync signal output 2. connects to the video connector side of one of the sync lines (for example, the vertical sync signal). 11 ddc1_ctlr ddc signal input 1. connects to the vga controller side of one of the ddc signals (for example, the bidirectional ddc_data serial line). 12 ddc1_conn ddc signal output 1. connects to the connector side of one of the ddc si gnals (for example, the bidirectional ddc_data serial line). 14 ddc2_ctlr ddc signal input 2. connects to the vga controller side of one of the ddc signals (for example, the bidirectional ddc_clk). 15 ddc2_conn ddc signal output 2. connects to the connector side of one of the ddc si gnals (for example, the bidirectional ddc_clk). package / pinout diagram note: this drawing is not to scale. 16-pin qsop 1 2 3 4 14 13 12 11 5 6 7 10 9 8 15 16 vcc ddc2_conn ddc2_ctlr vss ddc1_conn ddc1_ctlr sync2_conn vcc rgb1 rgb2 vss rgb3 sync1_conn sync1_ctlr sync2_ctlr vcc top v i ew
? 2002 california micro devices corp. all rights reserved. 02/14/02 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com 3 PACVGA100/101 ordering information note 1: parts are shipped in tape & reel form unless otherwise specified. specifications note 1: only one diode conducting at a time. part numbering information pins package ordering part number 1 part marking 16 qsop PACVGA100 PACVGA100q 16 qsop pacvga101 pacvga101q absolute maximum ratings parameter rating units supply voltage (v cc - v ss )6.0v diode forward dc current (note 1) 20 ma operating temperature range -40 to +85 c storage temperature range -65 to +150 c dc voltage at any channel input (v ss - 0.5) to (v cc + 0.5) v package power rating 800 mw standard operating conditions parameter rating units operating temperature range -40 to +85 c operating supply voltage (v cc - v ss ) pa c v g a 1 0 0 pa c v g a 1 0 1 5.0 3.3 to 5.0 v v
? 2002 california micro devices corp. all rights reserved. 4 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com 02/14/02 PACVGA100/101 specifications (cont?d) note 1: all parameters specified at t a =25c unless otherwise noted. note 2: these parameters guaranteed by design and characterization. note 3: from i/o pins to v p or v n only; v p bypassed to v n with 0.2 f ceramic capacitor. note 4: human body model per mil-std-883, method 3015, c discharge = 100pf, r discharge = 1.5k ?, v p = 5.0v, v n grounded. note 5: standard iec 61000-4-2 with c discharge = 150pf, r discharge = 330 ? , v p = 5.0v, v n grounded. note 6: these pins are not directly connected to the vga connector and therefore are not subject to direct esd strikes. electrical operating characteristics 1 symbol parameter conditions min typ max units tol r resistor absolute tolerance r/g/b termination resistor (r1) series termination resistor (r2) ddc pull-up resistor (r3) + 5 + 5 + 10 % % % tcr temperature coefficient of resistance (tcr) + 200 ppm/c v f diode forward voltage i f = 20ma 0.65 0.95 v v rb diode reverse breakdown voltage top diode (cathode connected to v cc ) bottom diode (anode connected to v ss ) 17.0 25.0 v v i leak channel leakage current + 0.1 + 1.0 a c in channel input capacitance at pins 2, 3, 5, 6, 10, 12 & 15 @ 1 mhz, v p =5v, v n =0v, v in =2.5v; note 2 applies 4.5 6 pf v esd esd protection 1) peak discharge voltage at pins 2, 3, 5, 6 10, 12 & 15, in system a) human body model, mil-std-883, method 3015 b) contact discharge per iec 61000-4-2 2) peak discharge voltage at pins 7, 9, 11 & 14 a) human body model, mil-std-883, method 3015 note 3 notes 2,4 notes 2,5 note 6 notes 2,4 + 15 + 8 + 4 kv kv kv v cp channel clamp voltage at pins 2, 3, 5, 6, 10, 12 & 15 positive transients negative transients @15kv esd hbm; notes 2 & 4 v p + 13.0 v n - 13.0 v v
? 2002 california micro devices corp. all rights reserved. 02/14/02 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com 5 PACVGA100/101 mechanical details qsop mechanical specifications PACVGA100/101 devices are packaged in 16-pin qsop packages. dimensions are presented below. for complete information on the qsop-16 package, see the california micro devices qsop package infor- mation document. * this is an approximate number which may vary. package dimensions for qsop-16 package dimensions package qsop (jedec name is ssop) pins 16 dimensions millimeters inches min max min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.20 0.30 0.008 0.012 c 0.18 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.81 3.98 0.150 0.157 e 0.64 bsc 0.025 bsc h 5.79 6.19 0.228 0.244 l 0.40 1.27 0.016 0.050 # per tube 100 pieces* # per tape and reel 2500 pieces controlling dimension: inches mechanical package diagrams e d h top view l end view c e b a a1 seating plane side view 5678 1234 12 11 10 9 16 15 14 13 pin 1 marking
|
